Espressif Systems /ESP32-P4 /CACHE /SYNC_L1_CACHE_PRELOAD_INT_ST

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Interpret as SYNC_L1_CACHE_PRELOAD_INT_ST

Description

L1-Cache Access Fail Interrupt status register

Fields

L1_ICACHE0_PLD_DONE_INT_ST	The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done.
L1_ICACHE1_PLD_DONE_INT_ST	The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done.
L1_ICACHE2_PLD_DONE_INT_ST	Reserved
L1_ICACHE3_PLD_DONE_INT_ST	Reserved
L1_DCACHE_PLD_DONE_INT_ST	The bit indicates the status of the interrupt that occurs only when L1-DCache preload-operation is done.
SYNC_DONE_INT_ST	The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done.
L1_ICACHE0_PLD_ERR_INT_ST	The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
L1_ICACHE1_PLD_ERR_INT_ST	The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
L1_ICACHE2_PLD_ERR_INT_ST	Reserved
L1_ICACHE3_PLD_ERR_INT_ST	Reserved
L1_DCACHE_PLD_ERR_INT_ST	The bit indicates the status of the interrupt of L1-DCache preload-operation error.
SYNC_ERR_INT_ST	The bit indicates the status of the interrupt of Cache sync-operation error.

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